Julian Bigelow’s Acrophobic Inchworm

or

Who Invented the So-Called Master-Slave Flip-Flop

In June, 1976, Julian Bigelow gave a talk at the International Research Conference on the History of Computing, at the Los Alamos Scientific Laboratory in which he recounted his experience, 30 years prior, as Chief Engineer for the development of the Electronic Computing Instrument at the Princeton Institute for Advanced Study – the IAS Machine.  One of many interesting developments that Bigelow recounted was his invention of what is now called the “master-slave” flip-flop.  Bigelow explained [1]:

With regard to fast arithmetical and gating circuitry, we knew that for shifting registers, binary counters, control logic, and much else we would need bistable electronic subunits in great abundance. As everybody knows today, a bistable circuit (or “binary cell”) is a device that has two stable states, changeable at will, to which may be assigned representation of the digit 0 or 1. . . . Circuits for doing this have been in the electrotechnical literature since 1919 when Eccles and Jordan first published such an arrangement consisting of two amplifying electron tubes cross connected so that either one makes the other go “off” when it itself is “on.” . . . These circuits are called “flip-flops” in much of the literature; our group preferred the term “toggle.”

⁝

We also studied the interdependence of these on the methods used to “gate in” and “gate out” information to the toggles. We found out what we should have known beforehand, that rate of digit flow among such binary cells depends on the gating techniques, and that with enough gating power commanding the cell to assume the desired state, that is to say, with directed gating, changeover delay can be made as brief as you please.

⁝

   Systematic use of such direct gating procedures to advance binary data locked in “sending” cells to “receiving” cells became the preferred technique used throughout the arithmetic unit, also in most of the logical control and in much elsewhere. Information was first locked in the sending toggle; then gating made it common to both sender and receiver, and then when securely in both, the sender could be cleared. Information was never “volatile” in transit; it was as secure as an acrophobic inchworm on the crest of a sequoia. We were amused to realize that the functioning was like a ship canal lock system and that the information advancing processes of the whole arithmetic unit resembled a complex clock escapement. [1, pp. 295–297] 

Above, I made the key sentence bold.  That is the essence of the so-called master-slave flip-flop which has been in use ever since.  Bigelow used three analogies to describe its operation:

1. Information is “as secure as an acrophobic inchworm on the crest of a sequoia”
2. Functioning is like “a ship canal lock system”
3. The process “resembled a complex clock escapement”

Nowhere does the term “master-slave” appear, and for good reason, that’s not how it works!

To understand how it works, I sketched Bigelow’s inchworm analogy alongside a double-rank toggle:

Figure 1: My Sketch of Julian Bigelow's Inchworm Analogy for the Functioning of the Toggles (Flip-Flops) Used in the IAS Machine

In the figure above, the sequence of events is depicted in five rows, running from top to bottom.  The left side shows Bigelow’s inchworm analogy, the center is annotated with Bigelow’s explanatory text, and the right side shows these events in a double-rank toggle (flip-flop).  Note that neither Bigelow nor the IAS engineers ever depicted toggles using cross-coupled NOR gates, I took this artistic liberty to make it more familiar to present-day readers.  It might be instructive to compare the sequence of events for both inchworm and toggles.  The following table is a textual description of Figure 1.

Time Step	Inchworm	Bigelow’s Description	Double-Rank Toggle
t=0	Front and rear halves firmly secured (all 10 legs) on left leaf.	Information was first locked in the sending toggle;	Sending toggle holding its state, receiving toggle isolated by open gate and not involved.
t=1	Front half moving to right leaf, rear half still secured to left leaf.	then gating…	Sending toggle still holding its state, interstage gate closed (enabled) to allow transfer.
t=2	Front half secured on right leaf, rear half still secured to left leaf.	made it common to both sender and receiver,	Sending toggle’s state now impressed upon receiving toggle.
t=3	Front half secured on right leaf, rear half released and moving to right leaf.	and then when securely in both,	Interstage gate opened (disabled), sending and receiving toggles still hold the same state.
t=4	Front and rear halves firmly secured (all 10 legs) on right leaf.	the sender could be cleared.	Sending toggle can be loaded with a new state without disturbing receiving toggle.

Documentary Record

In the first paragraph, you may have noticed I said, “his invention”, meaning Bigelow’s.  I feel justified in that statement because the author of the first published paper on this technique said as much [2].  The events go like this:

• 1946: Julian Bigelow was hired by von Neumann and appointed Chief Engineer for the IAS Machine [3].
• 1946-1951: One of Bigelow’s electrical engineers, Willis Ware, designed the IAS Machine’s binary counters using flip-flops based on Bigelow’s technique.
• 1953: Ware published a paper, based on his 1951 PhD dissertation, describing the technique.  In that paper, Ware said, “With each primary storage element, there is associated a secondary element whose only function is to remember the state of the primary element during any interval in which it is changing or is in a state of change. . . . This principle was first suggested by J. H. Bigelow, of the Electronic Computer Project, Institute for Advanced Study, Princeton, N.J.”

The next published paper I could find on the “double-rank” technique is in 1966 [4], 13 years later!  The author of that paper, Andrew Hall, credited Ware: “This report will be concerned with the synthesis of a particular class of fundamental mode sequential circuits which are called double rank sequential circuits which were originally described by Ware.”

Because the IAS Machine was paid for by the US government, Bigelow and his engineering team were required to publish a series of Interim Progress Reports describing their progress to date [5], [6], [7], [8], [9], [10], [11].  

The preface to the first report stated the purpose:

The express purpose of this report is to furnish contemporary advice to the Service regarding steps taken and contemplated toward the realization of an electronic computing instrument embodying the principles outlined in the Institute for Advanced Study report, dated 28 June 1946, entitled, "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument", by Burks, Goldstine and von Neumann*.

*Note that they reference the “Preliminary Discussion . . .” document and its famous authors. [12]

The first five reports were published every six months, the sixth and seventh reports stretching out much longer.  These reports provide a fascinating glimpse into the engineering decisions, both successes and failures, that went into the design.

In my next articles, I’ll explore the development of the double-rank flip-flop as described in the Interim Progress Reports.

Bibliography

[1] “Computer Development at the Institute for Advanced Study,” in A history of computing in the twentieth century : a collection of essays with introductory essay and indexes, in International Research Conference on the History of Computing (1976 : Los Alamos Scientific Laboratory). , New York: Academic Press, 1980. Accessed: May 15, 2023. [Online]. Available: http://archive.org/details/historyofcomputi0000inte

[2] W. H. Ware, “The Logical Principles of a New Kind of Binary Counter,” Proc. IRE, vol. 41, no. 10, pp. 1429–1437, Oct. 1953, doi: 10.1109/JRPROC.1953.274319.

[3] J. Bigelow, “Oral history interview with Julian Bigelow,” Jan. 20, 1971. Accessed: May 15, 2023. [Online]. Available: https://sova.si.edu//details/NMAH.AC.0196#ref84

[4] A. D. Hall Jr., “Synthesis Of Double Rank Sequential Circuits,” Princeton University, Department of Electrical Engineering, Digital Systems Laboratory, Technical Report 53, Dec. 1966. Accessed: Sep. 10, 2024. [Online]. Available: https://findingaids.princeton.edu/catalog/ENG013_c053

[5] Julian H. Bigelow, James H. Pomerene, Ralph J. Slutz, and Willis H. Ware, “Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 3, Jan. 1947. [Online]. Available: https://www.ias.edu/sites/default/files/library/pdfs/ecp/interimprogressr01inst.pdf

[6] Julian H. Bigelow, Theodore W. Hildebrandt, James H. Pomerene, Richard L. Snyder, Ralph J. Slutz, and Willis H. Ware, “Second Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 5, Jul. 1947. Accessed: May 12, 2023. [Online]. Available: https://www.ias.edu/sites/default/files/library/pdfs/ecp/secondinterimpro02inst.pdf

[7] Julian H. Bigelow, Theodore W. Hildebrandt, James H. Pomerene, Jack Rosenberg, Ralph J. Slutz, and Willis H. Ware, “Third Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 7, Jan. 1948. Accessed: May 12, 2023. [Online]. Available: https://www.ias.edu/sites/default/files/library/pdfs/ecp/thirdinterimprog03inst.pdf

[8] Julian H. Bigelow et al., “Fourth Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 10, Jul. 1948. Accessed: May 12, 2023. [Online]. Available: https://www.ias.edu/sites/default/files/library/pdfs/ecp/fourthinterimpro04inst.pdf

[9] Julian H. Bigelow et al., “Fifth Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 12, Jan. 1949. Accessed: May 12, 2023. [Online]. Available: http://cdm.itg.ias.edu/cdm/compoundobject/collection/coll12/id/329

[10] Charles V. L. Smith, “Sixth Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 14, Sep. 1951. Accessed: May 12, 2023. [Online]. Available: https://www.ias.edu/sites/default/files/library/pdfs/ecp/sixthinterimprog06inst.pdf

[11] Herman H. Goldstine, James H. Pomerene, and Charles V. L. Smith, “Final Interim Progress Report on the Physical Realization of an Electronic Computing Instrument,” Institute for Advanced Study, Princeton, New Jersey, 15, Jan. 1954. Accessed: May 12, 2023. [Online]. Available: https://www.ias.edu/sites/default/files/library/pdfs/ecp/finalprogressrep00inst.pdf

[12] A. W. Burks, H. H. Goldstine, and J. V. Neumann, Preliminary Discussion of the Logical Design of an Electronic Computing Instrument. Institute for Advanced Study, 1947.